The present invention relates to an information processing system which includes an arithmetic control unit fabricated on a single chip using very large scale integration.
With the recent developments in semiconductor techniques, the arithmetic control unit, which is the main component of an information processing system, can now be formed on a single chip by very large scale integration (sometimes referred to as VLSI for brevity hereinafter). When the arithmetic control unit is formed by VLSI, the performance of the unit may be improved, the unit may be made more compact, and the performance to price ratio may be improved. However, there are also limits on the number of pins the single chip package can accommodate as well as limits on power consumption, capacity and performance. VSLI application techniques require further development to solve these problems. One of the problems to be solved by such techniques may be summarized as follows. Input/output devices (sometimes referred to as I/O for brevity hereinafter) connected to the arithmetic control unit through input/output buses generally employ a data transfer width of 8 bits (1 byte). However, an I/O has recently been developed which employs a data transfer width of 16 bits for performing data transfer at a higher speed. Thus, the one-chip arithmetic control unit described above must be of a construction which permits smooth data transfer between these two different kinds of I/Os.
There is another problem. The one-chip arithmetic control unit utilized in the present invention is so constructed that control is performed by microprograms, and a memory for storing these microprograms (sometimes referred to as a ROM hereinafter) is externally connected to the chip due to limits imposed by the chip. Although it is possible to freely write into the externally-connected ROM, there are limits imposed on the selection of the ROM addresses. For example, when the operation code (OP code) of a user instruction is of 8-bit construction, up to 2.sup.8 =256 instructions may be prepared. In correspondence with these OP codes of 8 bits, microinstructions are stored in the 0 to 255 addresses of the externally-connected ROM. The microinstructions and the user instructions are different in bit construction and content. Accordingly, with an instruction of a complex function such as a floating instruction, it becomes impossible to translate one user instruction with only one microinstruction. In such a case, it becomes necessary to store an additional microinstruction necessary for translating a single user instruction in a certain address region of the ROM so that this address may be automatically selected. Further, it is not necessary to use all of the 2.sup. 8 =256 instructions; only some of them are usually used. Thus, when an OP code with no corresponding user instruction is designated by mistake (e.g., when the program overruns), it is necessary to detect that this OP code is an illegal instruction by the microinstruction processing portion of the system. One of the technical problems resulting from an arithmetic control unit formed on one chip is to find out how to perform these controls with satisfactory efficiency. In addition to this, it is desired not to fix the correspondence between the microprograms and the OP codes, but to vary the correspondence as required, so that the overall system can perform with an instruction system different from the original instruction system.
As logic functions within a chip increase, the number of connections for exterior signals increases. However, the number of external connection pins which may be formed on the package of the one-chip arithmetic control unit are limited. Another problem associated with the arithmetic control unit is, therefore, how to use this limited number of external connection pins to obtain more functions within the chip.